`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   12:50:05 11/28/2012
// Design Name:   DOWNSHIFT_ROM_CTR
// Module Name:   D:/Workspace/xilinx workspace/HFM_DETECTOR/dwnshift_rom_ctr_simu.v
// Project Name:  HFM_DETECTOR
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: DOWNSHIFT_ROM_CTR
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module dwnshift_rom_ctr_simu;

	// Inputs
	reg clk;
	reg rst;
	reg signed[15:0] in_data;
	reg signed[15:0] in_cos;
	reg signed[15:0] in_sin;

	// Outputs
	wire [6:0] addr_cos;
	wire [6:0] addr_sin;
	wire signed[31:0] out_r;
	wire signed[31:0] out_i;

	// Instantiate the Unit Under Test (UUT)
	DOWNSHIFT_ROM_CTR #(34, 7, 96, 16, 0) uut (
		.clk(clk), 
		.rst(rst), 
		.in_data(in_data), 
		.in_cos(in_cos), 
		.in_sin(in_sin), 
		.addr_cos(addr_cos), 
		.addr_sin(addr_sin), 
		.out_r(out_r), 
		.out_i(out_i)
	);

	integer i;
	always #10 clk = ~clk;

	initial begin
		// Initialize Inputs
		clk = 0;
		rst = 0;
		in_data = 0;
		in_cos = 0;
		in_sin = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		rst = 1;
      
		in_cos = 1;
		in_sin = -1;
		
		// Add stimulus here
		for(i=0;i<50;i=i+1)
			#20 in_data = i;
	end
      
endmodule

